Tutorial on Macro Design for Dynamic and Partial Reconfigurable Systems
Michael Hübner, Jürgen Becker
Laboratory for Information Processing Technology Dept. of Electrical Engineering and Information Technology
Universität Karlsruhe (TH)
Prof. Dr.-Ing. K. D. Müller-Glaser Prof. Dr.-Ing. J. Becker http://www.itiv.uni-karlsruhe.de
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Contents
• • • • • • •
Motivation Why dynamic and partial reconfiguration? Basics: Internal FPGA Structure Work package: Automotive Control System Why Communication Primitives (Bus-Macros)? Integration of Scheduler Summary
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Motivation
Student‘s skills in using novel technologies have to be extended to prepare them for future demands of the industry and academic research • Introduction of reconfigurable hardware architectures in an early phase • Highlighting the theoretical background with direct relation to reality • Hardware / Software Co-Design as an basic resource of knowledge for solving problems • Education with fundamental knowledge about hardware structure: • No secrets and “Black-Boxes” • No surprise between simulation and real integration • No border for new ideas • Theoretical part paired with “hands-on” tutorial and real applications • Feedback from industry and chip vendors: • Requirements to students • Novel solutions (architectures and tools) Tutorial with current architectures and tools, including novel academic results
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Why Dynamic and Partial Reconfiguration?
Data-Flow Graph A
Sequential Computation: tmp_1=A+B; tmp_2=C-D; tmp_3=E*F; tmp_4=tmp_1/tmp_2; tmp_5=tmp_1*tmp_4; tmp_6=tmp_4+tmp_3; Result=tmp_5-tmp_6;
B C +
D E
F x
Concurrent Computation: tmp_1=A+B; tmp_2=C-D; tmp_3=E*F; tmp_4=tmp_1/tmp_2; tmp_5=tmp_1*tmp_4; tmp_6=tmp_4+tmp_3; Result=tmp_5-tmp_6;
/ x +
Result = A+B/C-D+E*F-A+B/C-D+E*F; Parallelization for speeding up data-flow oriented functions
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Why Dynamic and Partial Reconfiguration?
A B +
Full parallel integration (also possible as ASIC design)
C D
E F X
A B +
C D
E F X
X
-
• Comparison of:
/
+
• Utilized area • Power consumption
/
Dataflow Scheduler
- • Data throughput
• Requiremtents (Scheduler, Recources etc.)
A B C D E F
Dataflow / Configuration Scheduler
Semi parallel integration (also possible as ASIC design)
A B C D
Operation
Dynamic Reconfigurable Hardware Dataflow / Configuration Scheduler
Operation Operation Operation
Dynamic Reconfigurable Hardware
E F
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Why Dynamic and Partial Reconfiguration?
A B C D E F
Dataflow / Configuration Scheduler
A B C D
Operation
Dynamic Reconfigurable Hardware Dataflow / Configuration Scheduler
Operation Operation Operation
Dynamic Reconfigurable Hardware
E F
Hardware / Software Trade-Off
Performance / Power Consumption / Costs Trade-Off
„Real World” example in „Hands-On“ Tutorial
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Why Dynamic and Partial Reconfiguration?
Substitution
Active Function Window Lift
Active Function
Central Lock
Active Function
Boarding Assistance
Active Function Seat Control
Active Function
Rear Mirror
Active Function
Parking Assistance
Active Function
Roof Window
Active Function
Distance Assistance
Substitution only allowed if function is inactive. (e.g. Active = Powered Actuators)
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Why Dynamic and Partial Reconfiguration?
Window leveler Window leveler 11 Window leveler Window leveler 22 Window leveler Window leveler 33 Window leveler Window leveler 44
All necessary modules resident on FPGA: Window leveler 1 Window leveler 1 Window leveler 1 Window leveler 1
Seat control Seat control 11 Seat control Seat control 22
Only actually used modules configured on FPGA:
Complete Power dissipation: 2133.8mW
Empty Empty Complete Power
dissipation: Window leveler 1 1703.6mW Window leveler 1 Window leveler 1 Window leveler 1
Reconfiguration on demand
Empty Empty Complete Power
dissipation: Seat control 2 1757mW Seat control 1 Window leveler 1 Window leveler 1
Seat control 1
Seat control 2
While Reconfiguration: 1797.5 mW
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Why Dynamic and Partial Reconfiguration?
Config. Block B Config. Block A Config. Block B Config. Block A
Trade-off
Reconfiguration on Demand
– High static and dynamic Power Consumption – No Run-Time Reconfiguration Management necessary
– Optimal size of FPGA (depends on the size of the greatest Module to implement) – Less static and dynamic Power Consumption but additional Power loss by increased external Memory – Caution: Additional Power Consumption while Reconfiguration
(Median Power Dissipation increases with the Frequency of Reconfiguration)
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Basics: Internal FPGA Structure
A B
0 0 1 1 0 0 1 1
C
0 1 0 1 0 1 0 1
Q
0 0 0 0 0 0 0 1
Synthesis, Place & Route Configuration Access Port Configuration Memory A B C
Lookuptable
Address VCC
0 0 0 0 1 1 1
Q
Hardware Layer
1
GND
Logic Resources
Basic knowledge helps to understand HDL and why results sometimes can be surprising
Routing Resources
To Configuration Memory
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Work package: Automotive Control System
Search Slot Backup state Start Reconfiguration Restore state
Run-time Module Controller
µController (MicroBlaze) Start address End address
Buffer
Buffer
I/O (e.g. CAN)
CANInterface
Module C Module D
Bus Com 0
ID 0
Module A
Bus Com 1
ID 1
Module B
Module E
Bus Com 3
State State! Last Bus-Word Save - Data
BootCPLD
FlashMemory
Bootstream
State - Data
Buffer
Bus Com 2
ID 2
ID 3
Decompressor Unit (LZSS)
Arbiter
Bus-Macro
Slotstreams
ICAP
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MB MD
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Work package: Automotive Control System
Search Slot Backup state Start Reconfiguration Restore state
Everything is included!
Run-time Module Controller
µController (MicroBlaze)
Buffer
Buffer
I/O (e.g. CAN)
CANInterface
Module C Module D
Bus Com 0
ID 0
Module A
Bus Com 1
ID 1
Module B
Module E
Bus Com 3
BootCPLD
FlashMemory
Bootstream
Buffer
Bus Com 2
ID 2
ID 3
Decompressor Unit (LZSS)
Arbiter
Bus-Macro
Slotstreams
ICAP
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Real Car Application / Integration
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Why Communication Primitives (Bus-Macros)?
Function A
add FPGA
substitute
Function B
Config. Block A
Block unconfigured
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Config. Block B
Config. Block C
Block pre-configured
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Config. Block D
Why Communication Primitives (Bus-Macros)?
External wiring: • Causes special PCB design • Unflexible if modules have to be changed (size and I/O) • Possible conflicts caused by signal delay
Module B
Module C
Module A
Module D
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Why Communication Primitives (Bus-Macros)?
Signal lines eventually open or connected to composit signal level
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Module A
Module C
Module B
Module D
Why Communication Primitives (Bus-Macros)?
Interface (Macro)
Geneneralized routing points (for each module)with fixed the Usage of interfaces (macros) enables routing enables possibility of interchangeable module positions connection points for all modules
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Module A Module A
Module B Module B
Module D Module D
Module C Module C
Basic Communication Elements
• Example configuration of the Input-Macro:
Look-Up-Tables connect through Input-Signal
Output 1
Output 2
4
4
CLB
4 4
Input 1 Input 2
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Example Design: Macro for Module Connection
Example Implementation of Input-Macro on FPGA (one CLB row, one direction):
Connection to the respective modules
Module 0
8
Module 1
8
Module 2
8
Module 3
8 8
8
Data/ Signals from Bus-Arbiter/ RT-MC
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Programming on „Hardware Resource Level“
LUT programmed to pass trough signals (e.g. D=G4)
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Integration of Scheduler
• Tasks of the Run-Time System – Processing of messages
• Transfer of messages to the modules • Transfer of messages from the modules • Buffering of messages
– Rekonfiguration management
• Choice of reconfiguration slot • Storing of Context data • Start of dynamic and partial reconfiguration • Restoring of Context data
– Management of FPGA Slots and Module Data
• Management of slot allocation • Management of the data buffer for each module • Management of Context data
•
Requirements to the Run-Time System – Messages must be transferred within the required time – Messages must be transferred in the right order
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Complete Integrated System
CANAnbindung
MicroBlaze in r 3 (Laufzeitsystem) Slot 0 Slot 1 Slot 2 Slot e
Tes t
al c a
r!
ICAP/ Dekompressor
Arbiter
Bussystem
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Summary
Tutorial with „red thread“:
• Motivation: Why dynamic reconfiguration is a solution for future systems • Basics of FPGA: Knowledge of hardware structures • Work Package: Real scenario from automotive industry • Introduction of communication primitives • Marco design with state of the art FPGA and tools • Programming of Scheduler • System integration and test in real car
Two week „Hands-On“ Tutorial:
Theoretical part:
• • • • Graph Theory Synthesis of hardware modeled in HDL Scheduling algorithms Technology Mapping
Practical part:
• • • • • • Introduction: Hardware Design Tools Basic Systems: Integration on real hardware Macro Design Development of partitioned system Scheduler development Integration of complete system
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Thanks for your attention!
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